The disclosure relates generally to integrated circuits. More particularly, various aspects relate to overlay analysis, modeling and optimization of overlay in integrated circuits.
Developing and testing integrated circuit (IC) devices, also referred to as semiconductor devices, involves designing, manufacturing and testing these devices according to desired operating parameters. Quality assurance has been a concern in the development, fabrication and testing of IC devices, but is particularly important as these devices become ever more complex.
Ever increasing pattern density and more complicated lithography techniques require a greater understanding of the placement and locational relationship between components in distinct levels of the IC. This relationship, generally referred to as overlay, can be used to predict and modify (if necessary) masking processes in the formation of an IC. However, current approaches for analyzing overlay fail to be predictive in nature, lacking models for upcoming processing nodes. These current approaches also fail to accurately characterize topographical features, and as such, can lead to costly and unnecessary late-stage modification of masking and formation processes.